The present invention relates to a semiconductor device, and more particularly to a side wall contact on a side wall of a contact hole formed in an inter-layer insulator over a semiconductor substrate as well as a method of forming the same.
As the degree of the integration of large scale integrated circuits has been on the increase, each device as integrated has been scaled down. In these circumstances, it is important how a margin between devices is secured without deterioration of a high yield. For example, a self-align-contact or a side wall contact are typical techniques for securing the same.
The side wall contact technique is applicable to various semiconductor devices such as a dynamic random access memory. A conventional method of forming a memory cell structure of the dynamic random access memory will be described. FIGS. 1A through 1E are fragmentary cross sectional elevation views illustrative of a conventional method of forming a conventional memory cell structure of a dynamic random access memory, wherein said conventional memory cell structure has a conventional side wall contact structure.
With reference to FIG. 1A, field oxide films 2 are selectively formed on a passive region of a p-type silicon substrate 1 to define an active region. Gate oxide films 3 are formed on a part of the field oxide film 2 and the active region of the silicon substrate 1. First and second gate electrodes 4 of a polysilicon film which also act as word lines are formed on the gate oxide film 3. The gate electrode 4 is positioned over a channel region in the active region of the substrate 1. Source and drain diffusion regions 5 of nxe2x88x92-type are selectively formed by self-alignment on the active regions other than the channel region of the substrate 1, whereby the source and drain diffusion regions 5 define the channel region. A first inter-layer insulator 6 is entirely formed which extends over the passive regions and the active regions of the substrate 1 so that the first inter-layer insulator 6 covers the field oxide film 2, the gate electrodes 4 and the source and drain diffusion regions 5.
With reference to FIG. 1B, a second inter-layer insulator made of boro-phospho silicate glass from tetraethyl orthosilicate (TEOS) is formed on the first inter-layer insulator 6. The second inter-layer insulator is much thicker than the first inter-layer insulator 6. Although illustration is omitted, bit contacts and bit lines arc formed. The bit contacts provide electrical connections between the bit lines and the source and drain regions. The bit contacts and the bit lines are formed by well known techniques of photo-lithography and subsequent dry etching. The bit lines may be made of a second polysilicon. A third inter-layer insulator made of boro-phospho silicate glass from tetraethyl orthosilicate (TEOS) is formed on the second inter-layer insulator and over the bit lines, whereby an inter-layer insulator 7 of the second and third inter-layer insulators is then formed. A fourth inter-layer insulator 8 is formed on the inter-layer insulator 7. The fourth inter-layer insulator 8 may be made of a different insulating material, such as silicon dioxide, from the second and third inter-layer insulators. The fourth inter-layer insulator 8 is much thinner than the inter-layer insulator 7. The thickness of the fourth inter-layer insulator 8 is, for example, in the range of about 150-200 nanometers. A photo-resist is applied on the fourth inter-layer insulator 8 and then subjected to exposure and subsequent development to form a photo-resist pattern 10 over the fourth inter-layer insulator 8.
With reference to FIG. 1C, a dry etching process is carried out by use of the photo-resist pattern 10 to selectively etch laminations of the fourth inter-layer insulator 8, the inter-layer insulator 7 and the and the first inter-layer insulator 6, whereby a contact hole 11 is formed which penetrates the laminations of the fourth inter-layer insulator 8, the inter-layer insulator 7 and the first inter-layer insulator 6, so that a part of the diffusion region 5 is shown through the contact hole 11. The contact hole 11 has a depth of about 1200 nanometers. An oxide film 12-a made of non-doped silicate glass (NSG) from TEOS is entirely deposited so that the oxide film 12-a extends on a bottom and a side wall of the contact hole as well as on the surface of the fourth inter-layer insulator 8.
With reference to FIG. 1D, an etch back to the oxide film 12-a is carried out by use of a dry etching process for the purpose of removing the bottom part of the oxide film 12-a on the diffusion region 5 and also the top parts of the oxide film 12-a on the fourth inter-layer insulator 8. It is necessary to completely remove the bottom part of the oxide film 12-a so that no residual part of the oxide film 12-a remains on the bottom of the contact hole 11, whereby the part of the diffusion region 5 is shown through the contact hole
If a diameter of the top portion of the contact hole 11 is about 0.3 micrometers, then an aspect ratio of the contact hole 11 is about 4. This high aspect ratio of the contact hole causes a micro-loading effect which reduces an etching rate of the oxide film 12-a in the deep region of the contact hole 11. Namely, the micro-loading effect causes the oxide film 12-a over the contact hole 11 to be higher in etching rate than in the deep region of the contact hole 11. This means that, in order to exactly etch the bottom portion of the oxide film 12-a, it is necessary to allow an over-etching to the upper portion of the oxide film 12-a over the contact hole 11 since the upper portion of the oxide film 12-a is higher in etching rate than the deep portion of the oxide film 12-a. 
This over-etching to the upper portion of the oxide film 12-a means that not only the top portion of the oxide film 12-a on the surface of the fourth inter-layer insulator 8 but also a shallow portion of the oxide film 12-a positioned in a shallow region of the contact hole 11 are etched, whereby the fourth inter-layer insulator 8 reduces in thickness and thus is made thin, and further the top portion of the oxide film 12-a drops in level so that the top level of the etched oxide film 12-a becomes lower than the bottom level of the fourth inter-layer insulator 8.
Namely, in order to exactly etch the bottom portion of the oxide film 12-a, the over-etching is continued until the shallower portion of the oxide film 12-a in the shallower region of the contact hole 11 is etched, whereby the oxide film 12-a is made into a side wall contact 12-b which extends on the side wall of the contact hole 11 except on a shallower region of the contact hole 11. The top portion of the side wall contact 12-b lies lower in level than the bottom of the fourth inter-layer insulator 8, whereby an upper region of the inter-layer insulator 7 is shown between the top portion of the side wall contact 12-b and the bottom of the fourth inter-layer insulator 8.
This is caused by the micro-loading effect in the etch-back process under the condition of the high aspect ratio of the contact hole. As the aspect ratio of the contact hole is large, then the micro-loading effect is remarkable, whereby the necessary over-etching amount for completely removing the bottom portion of the oxide film 12-a from the bottom of the contact hole 11 is increased, thereby increasing the amount of drop in level of the top of the side wall contact 11 or the shown region of the inter-layer insulator 7.
A storage electrode 13 made of polysilicon is then formed which fills the contact hole 11 and extends over the contact hole 11 and the fourth inter-layer insulator 8. As the requirement for scaling down the storage capacitor increases, it is possible that an alignment of the storage electrode 13 to the contact hole will deteriorate so that a part of the top portion of the contact hole 11 is shown without complete coverage of the top portion of the contact hole 11 by the storage electrode 13.
As the next process, a wet etching with a hydrofluoric acid etchant in a hemi-spherical grain(HSG) technique is carried out to increase the roughness of the surface of the storage electrode 13, thereby increasing the surface area of the storage electrode 13 for increasing the capacitance without increasing the occupied area of the storage capacitor. This wet etching process may also cause the shown part of the inter-layer insulator 7 to be etched with the etchant, whereby an etched hollow portion 14 is formed in the shown part of the inter-layer insulator 7 between the edge of the fourth inter-layer insulator 8 and the top of the side wall contact 12-b. 
With reference to FIG. 1E, a capacitive dielectric film 15 is formed on the surface of the storage electrode 13. A plate electrode 16 is then formed on the capacitive dielectric film 15 so that the capacitive dielectric film 15 is sandwiched by the storage electrode 13 and the plate electrode 16. However, the etched hollow portion 14 may remarkably deteriorate the coverage of the capacitive dielectric film 15 and the plate electrode 16. This deterioration in coverage of the capacitive dielectric film 15 and the plate electrode 16 may increase the leakage of current through the capacitive dielectric film 15.
In order to settle the above problem caused by the etched hollow portion, it is proposed to increase the thickness of the fourth inter-layer insulator 8, for example, about 300-350 nanometers, so that the bottom level of the fourth inter-layer insulator 8 will lie below the top of the side wall contact 12-b to form an overlapped margin between the top portion of the side wall contact 12-b and the fourth inter-layer insulator 8, whereby no shown part is formed of the inter-layer insulator 7. This increase in thickness of the fourth inter-layer insulator 8, however, causes the other problem, in that there is an increase in the aspect ratio when the contact hole is formed. This high aspect ratio exacerbates the micro-loading effect.
In the above circumstances, it is necessary to develop a novel method of forming a side wall contact on a side wall of a contact hole with a high aspect ratio free from the above problems.
Accordingly, it is an object of the present invention to provide a novel method of forming a side wall contact on a side wall of a contact hole with a high aspect ratio free from the above problems.
It is a further object of the present invention to provide a novel method of forming a side wall contact on a side wall of a contact hole with a high aspect ratio for securing a sufficient overlap margin between the top of the side wall contact and a top inter-layer insulator.
It is a further object of the present invention to provide a novel method of forming a side wall contact on a side wall of a contact hole with a high aspect ratio for avoiding any further increase in total thickness of the inter-layer insulator.
It is yet a further object of the present invention to provide a novel side wall contact structure on a side wall of a contact hole with a high aspect ratio free from the above problems.
It is a further object of the present invention to provide a novel side wall contact on a side wall of a contact hole with a high aspect ratio for securing a sufficient overlap margin between the top of the side wall contact and a top inter-layer insulator.
It is a further object of the present invention to provide a novel side wall contact on a side wall of a contact hole with a high aspect ratio for avoiding any further increase in total thickness of the inter-layer insulator.
The present invention provides a method of forming a side wall contact on a side wall of a contact hole in an inter-layer insulator structure by an etch-back process. The method comprises the steps of: forming a first insulation film on a top insulation layer of the inter-layer insulator structure at least before forming a second insulation film, so that the second insulation film extends on the side wall and a bottom of the contact hole as well as on a surface of the first insulation film, wherein the first insulation film is higher in etching selectivity than the top insulation layer of the inter-layer insulator structure as well as the second insulation film is lower in etching selectivity than the top insulation layer of the inter-layer insulator structure, and the second insulation film is lower in etching selectivity than the first insulation film; and carrying out an etch back process in over-etching to the second insulation film by use of the first insulation film as an etching stopper so as to completely remove a bottom portion of the second insulation film on the bottom of the contact hole, thereby to form a side wall contact on the side wall of the contact hole, so that the side wall contact has a top level which lies between bottom and top levels of the top insulation layer.
The second present invention provides a method of forming a side wall contact on a side wall of a contact hole in an inter-layer insulator structure by an etch-back process, the method comprising the steps of: forming an etching stopper on a top insulation layer of the inter-layer insulator structure at least before forming a side wall contact film, so that the side wall contact film extends on the side wall and a bottom of the contact hole as well as on a surface of the etching stopper, wherein the side wall contact film is lower in etching selectivity than the top insulation layer of the inter-layer insulator structure; and carrying out an etch back process in over-etching to the side wall contact film so as to completely remove a bottom portion of the side wall contact film on the bottom of the contact hole, thereby forming a side wall contact on the side wall of the contact hole, so that the side wall contact has an over-lap margin with the top insulation layer.
The third present invention provides a side wall contact structure comprising: a contact hole in an inter-layer insulator structure having a top insulation layer; a first insulation film on a surface of the top insulation layer of the inter-layer insulator structure, wherein the first insulation film is made of a first insulation material which is higher in etching selectivity than the top insulation layer of the inter-layer insulator structure; and a side wall contact extending on the side wall of the contact hole, so that the side wall contact has a top level which lies between bottom and top levels of the top insulation layer, wherein the side wall contact is made of a second insulating material which is lower in etching selectivity than the top insulation layer of the inter-layer insulator structure and also the second insulating material is lower in etching selectivity than the first insulating material.
The fourth present invention provides a side wall contact structure comprising: a contact hole in an inter-layer insulator structure having a top insulation layer; and a side wall contact extending on the side wall of the contact hole, so that the side wall contact has a top level which lies between bottom and top levels of the top insulation layer, wherein the side wall contact is made of a second insulating material which is lower in etching selectivity than the top insulation layer of the inter-layer insulator structure.
The above and other objects, features and advantages of the present invention will be apparent from the following descriptions.